In existing integrated circuits, an interconnection between an upper layer and a lower layer can be generally achieved by using one or more contact vias. A specific process for forming a contact via can include the following steps. Firstly, a dielectric layer can be deposited. Then, a through hole can be formed in the dielectric layer by using photolithography technique and an etching process. Next, a barrier layer and a seed layer can be sequentially formed by using a physical vapor deposition (PVD) process. Then the through hole can be filled by using an electro chemical plating (ECP) method. Finally, a top surface of the filled through hole can be planarized by using a chemical mechanical polishing (CMP) method.
However, during the deposition process for forming the barrier layer, a portion of the barrier layer can be deposited on the bottom of the through hole, which can increase the resistance of the contact via. Accordingly, it is desired to provide a method to reduce the resistance of the contact via.